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SystemVerilog for design : a guide to using SystemVerilog for hardware design and modeling /

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SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs...

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Bibliographic Details
Main Author: Sutherland, Stuart, 1953-
Corporate Author: SpringerLink (Online service)
Other Authors: Davidmann, Simon, Flake, Peter
Format: eBook
Language:English
Published: Norwell, Mass. : Kluwer Academic, [2004]
Subjects:
Verilog (Computer hardware description language)
Electronic digital computers > Design and construction.
Computer simulation.
Electronic books.
Online Access:Connect to the full text of this electronic book
Table of Contents:
  • 1: Introduction to SystemVerilog
  • 2: SystemVerilog Literal Values and Built-in Data Types
  • 3: SystemVerilog User-Defined and Enumerated Data Types
  • 4: SystemVerilog Arrays, Structures and Unions
  • 5: SystemVerilog Procedural Blocks, Tasks and Functions
  • 6: SystemVerilog Procedural Statements
  • 7: Modeling Finite State Machines with SystemVerilog
  • 8: SystemVerilog Design Hierarchy
  • 9: SystemVerilog Interfaces
  • 10: A Complete Design Modeled with SystemVerilog
  • 11: Behavioral and Transaction Level Modeling
  • Appendix A: The SystemVerilog Formal Definition (BNF)
  • Appendix B: A History of SUPERLOG, The Beginning of SystemVerilog.