rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: SystemVerilog for design
    sub title: a guide to using SystemVerilog for hardware design and modeling
  title info:
    title: System Verilog for design
  name:
    name part: Sutherland, Stuart
    name part: 1953-
    role:
      role term: creator
  name:
    name part: Davidmann, Simon.
  name:
    name part: Flake, Peter.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  genre: Electronic books.
  origin info:
    place:
      place term: mau
    date issued: 2004
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource (xxviii, 374 pages) : illustrations.
  abstract: SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, SystemVerilog for Design, addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, SystemVerilog for Verification, covers the second aspect of SystemVerilog.
  table of contents: 1: Introduction to SystemVerilog -- 2: SystemVerilog Literal Values and Built-in Data Types -- 3: SystemVerilog User-Defined and Enumerated Data Types -- 4: SystemVerilog Arrays, Structures and Unions -- 5: SystemVerilog Procedural Blocks, Tasks and Functions -- 6: SystemVerilog Procedural Statements -- 7: Modeling Finite State Machines with SystemVerilog -- 8: SystemVerilog Design Hierarchy -- 9: SystemVerilog Interfaces -- 10: A Complete Design Modeled with SystemVerilog -- 11: Behavioral and Transaction Level Modeling -- Appendix A: The SystemVerilog Formal Definition (BNF) -- Appendix B: A History of SUPERLOG, The Beginning of SystemVerilog.
  note: by Stuart Sutherland, Simon Davidmann, Peter Flake ; foreword by Phil Moorby.
  subject:
    topic: Verilog (Computer hardware description language)
  subject:
    topic: Electronic digital computers
    topic: Design and construction
  subject:
    topic: Computer simulation
  subject:
    topic: Computer simulation
  subject:
    topic: Electronic digital computers
    topic: Design and construction
  subject:
    topic: Verilog (Computer hardware description language)
  classification: TK7885.7 .S875 2004eb
  classification: 621.39/2
  classification: 54.53
  related item:
    title info:
      title: SystemVerilog for design
    name:
      name part: Sutherland, Stuart, 1953-
    identifier: (DLC) 2004271791
    identifier: (OCoLC)54973856
  identifier: 9781475766820 (electronic bk.)
  identifier: 1475766823 (electronic bk.)
  identifier: 1402075308
  identifier: 9781402075308
  identifier: http://proxy.library.tamu.edu/login
  record info:
    record content source: GW5XE
    record creation date: 140711
    record change date: 20260420201223.0
    record identifier: in00003553134
    language of cataloging:
      language term: eng