http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
VLSI chip design with the hardware description language VERILOG
an introduction based on a large RISC processor design
1 online resource (xiv, 358 pages) : illustrations.
1 online resource (1 computer disk (3 1/2 in.)
This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.
Accompanied by floppy disk available from the Issue Desk.
Ulrich Golze ; with Peter Blinzer ... [and others].
Includes bibliographical references (pages [347]-351) and index.
Verilog (Computer hardware description language)