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VLSI chip design with the hardware description language VERILOG : an introduction based on a large RISC processor design /

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This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on...

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Bibliographic Details
Main Author: Golze, Ulrich, 1948-
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: Berlin ; New York : Springer, [1996]
Subjects:
Integrated circuits > Very large scale integration > Computer-aided design.
Verilog (Computer hardware description language)
RISC microprocessors > Computer-aided design.
Entwurf.
Prozessor.
RISC.
VERILOG.
VLSI.
Electronic books.
Online Access:Connect to the full text of this electronic book
Description
Summary:This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.
Physical Description:1 online resource (xiv, 358 pages) : illustrations.
1 online resource (1 computer disk (3 1/2 in.)
Bibliography:Includes bibliographical references (pages [347]-351) and index.
ISBN:9783642610011 (electronic bk.)
3642610013 (electronic bk.)