rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Efficient Path Delay Test Generation with Boolean Satisfiability
  name:
    name part: Bian, Kun
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Walker, Duncan
    role:
      role term: thesis advisor.
  name:
    name part: Khatri, Sunil P.
    role:
      role term: thesis advisor.
  name:
    name part: Texas A & M University
    role:
      role term: degree granting institution.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: txu
    date issued: 2014
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource.
  abstract: This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver. Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don't Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don't Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure. The electronic version of this dissertation is accessible from http://hdl.handle.net/1969.1/151900
  note: by Kun Bian.
  note: "Major Subject: Computer Engineering."
  note: Includes vita.
  note: Doctor of Philosophy Texas A & M University 2013 http://hdl.handle.net/1969.1/151900
  note: Includes bibliographical references.
  note: Text (Dissertation)
  subject:
    topic: Major Computer Engineering
  subject:
    topic: delay test
  subject:
    topic: ATPG
  subject:
    topic: SAT
  identifier: http://hdl.handle.net/1969.1/151900
  record info:
    record content source: TXA
    record creation date: 140609
    record change date: 20151206101421.0
    record identifier: in00003481787
    language of cataloging:
      language term: eng