rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: High Performance Interconnect System Design for Future Chip Multiprocessors
  name:
    name part: Wang, Lei
    role:
      role term: creator
    role:
      role term: author.
  name:
    name part: Kim, Eun Jung
    role:
      role term: thesis advisor.
  name:
    name part: Texas A & M University
    role:
      role term: degree granting institution.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: txu
    date issued: 2013
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource.
  abstract: Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP architectures. NOC must be carefully designed to meet constraints of power and area, and provide ultra low latencies and high throughput. In this research, we explore different techniques to design high performance NOC. First, existing NOCs mostly use Dimension Order Routing (DOR) to determine the route taken by a packet in unicast traffic. However, with the development of diverse applications in CMPs, one-to-many (multicast) and one-to-all (broadcast) traffic are becoming more common. Current unicast routing cannot support multi-cast and broadcast traffic efficiently. We propose Recursive Partitioning Multicast (RPM) routing and a detailed multicast wormhole router design for NOCs. RPM allows routers to select intermediate replication nodes based on the global distribution of destination nodes. This provides more path diversities, thus achieves more bandwidth-efficiency and finally improves the performance of the whole network. Second, as feature size is shrinking, wires are becoming abundant resources available in NOC. Since NOC can benefit from high wire density due to no limits on the number of pins and faster signaling rates, it is very critical in the NOC router design to find a way that fully utilizes the wire resources to provide high performance. We propose an Adaptive Physical Channel Regulator (APCR) for NOC routers to exploit huge wiring resources. The flit size in an APCR router is less than the physical channel width (phit size) to provide finer granularity flow control. An APCR router allows flits from different packets or flows to share the same physical channel in a single cycle. The three regulation schemes (Monopolizing, Fair-sharing and Channel-stealing) intelligently allocate the output channel resources considering not only the availability of physical chan…
  note: by Lei Wang.
  note: "Major Subject: Computer Engineering"
  note: Includes vita.
  note: Doctor of Philosophy Texas A & M University 2013 http://hdl.handle.net/1969.1/149541
  note: Includes bibliographical references.
  note: Text (Dissertation)
  subject:
    topic: Major Computer Engineering
  subject:
    topic: Network-On-Chip
  subject:
    topic: Chip Multiprocessors
  identifier: http://hdl.handle.net/1969.1/149541
  record info:
    record content source: TXA
    record creation date: 140117
    record change date: 20151206091203.0
    record identifier: in00003426004
    language of cataloging:
      language term: eng