Cover Image

Resilient architecture design for voltage variation /

Bibliographic Details
Main Author: Janapa Reddi, Vijay
Other Authors: Gupta, Meeta Sharma
Format: eBook
Language:English
Published: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, [2013]
Series:Synthesis lectures in computer architecture ; #22.
Subjects:
Electric power system stability.
Microprocessors > Power supply.
TECHNOLOGY & ENGINEERING / Electrical.
di/dt
error correction
error detection
error recovery
inductive noise
power delivery networks
power supply noise
transient errors
voltage emergencies
voltage noise
voltage smoothing
Online Access:Connect to the full text of this electronic book
Table of Contents:
  • 1. Introduction
  • 1.1 Parameter variations
  • 1.2 Worst-case design
  • 1.3 Design for the typical case
  • 1.4 Scope of the book
  • 2. Modeling voltage variation
  • 2.1 A quick primer
  • 2.2 The power-delivery network (PDN) subsystem
  • 2.2.1 Distributed grid model
  • 2.2.2 Impulse-response-based model
  • 2.2.3 Sparse grid model
  • 2.3 Summary
  • 3. Understanding the characteristics of voltage variation
  • 3.1 Current pulses
  • 3.2 PDN characteristics
  • 3.3 Microarchitectural events
  • 3.4 Program behavior
  • 3.5 Summary
  • 4. Traditional solutions and emerging solution forecast
  • 4.1 Traditional static techniques
  • 4.1.1 Voltage margins
  • 4.1.2 Decoupling capacitors
  • 4.1.3 Floorplanning
  • 4.2 Toward dynamic techniques
  • 4.2.1 Tolerance
  • 4.2.2 Avoidance
  • 4.2.3 Elimination
  • 4.3 Summary
  • 5. Allowing and tolerating voltage emergencies
  • 5.1 Error detection
  • 5.2 Global recovery
  • 5.2.1 Checkpoint recovery
  • 5.2.2 Delayed commit and rollback
  • 5.3 Local recovery
  • 5.4 Razor
  • 5.5 Summary
  • 6. Predicting and avoiding voltage emergencies
  • 6.1 Sensor-based throttling
  • 6.1.1 Design
  • 6.1.2 Challenges
  • 6.2 Event-based throttling
  • 6.2.1 Single-event predictors
  • 6.2.2 Signature-based prediction
  • 6.3 Summary
  • 7. Eliminating recurring voltage emergencies
  • 7.1 Opportunities and challenges
  • 7.1.1 Opportunities
  • 7.1.2 Challenges
  • 7.2 Compiler techniques
  • 7.2.1 Static compiler
  • 7.2.2 Dynamic compiler
  • 7.3 Thread scheduling
  • 7.3.1 Interthread interference
  • 7.3.2 Voltage smoothing
  • 7.3.3 Benefits and tradeoffs
  • 7.4 Summary
  • 8. Future directions on resiliency
  • 8.1 System-level resiliency
  • 8.2 Application-level resiliency
  • Bibliography
  • Authors' biographies.