Communication reliability in network on chip designs /

Bibliographic Details
Main Author: Kumar, Reeshav
Other Authors: Choi, Seong Gwan (Thesis advisor)
Format: Thesis eBook
Language:English
Published: [College Station, Tex.] : [Texas A&M University], [2012]
Subjects:
Online Access:Link to OAK Trust copy

MARC

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099 |a 2011  |a Thesis  |a 1969.1/ETD-TAMU-2011-08-10080 
100 1 |a Kumar, Reeshav. 
245 1 0 |a Communication reliability in network on chip designs /  |c by Reeshav Kumar. 
264 1 |a [College Station, Tex.] :  |b [Texas A&M University],  |c [2012] 
300 |a 1 online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
500 |a "Major Subject: Electrical Engineering" 
588 |a Description from author supplied metadata (automated record created 2012-10-22 13:24:58). 
502 |b Master of Science  |c Texas A&M University  |d 2011  |o http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10080 
504 |a Includes bibliographical references. 
516 |a Text (Thesis) 
520 3 |a The performance of low latency Network on Chip (NoC) architectures, which incorporate fast bypass paths to reduce communication latency, is limited by crosstalk induced skewing of signal transitions on link wires. As a result of crosstalk interactions between wires, signal transitions belonging to the same flit or bit vector arrive at the destination at different times and are likely to violate setup and hold time constraints for the design. This thesis proposes a two-step technique: TransSync- RecSync, to dynamically eliminate packet errors resulting from inter-bit-line transition skew. The proposed approach adds minimally to router complexity and involves no wire overhead. The actual throughput of NoC designs with asynchronous bypass designs is evaluated and the benefits of augmenting such schemes with the proposed design are studied. The TransSync, TransSync-2-lines and RecSync schemes described here are found to improve the average communication latency by 26%, 20% and 38% respectively in a 7X7 mesh NoC with asynchronous bypass channel. This work also evaluates the bit-error ratio (BER) performance of several existing crosstalk avoidance and error correcting schemes and compares them to that of the proposed schemes. Both TransSync and RecSync scheme are dynamic in nature and can be switched on and off on-the-fly. The proposed schemes can therefore be employed to impart unequal error protection (UEP) against intra-flit skewing on NoC links. In the UEP, a larger fraction of the energy budget is spent in providing protection to those parts of the data being transmitted on the link which have a higher priority, while expending smaller effort in protecting relatively less important parts of the data. This allows us to achieve the prescribed level of performance with lower levels of power. The benefits of the presented technique are illustrated using an H.264 video decoder system-on-chip (SoC) employing NoC architecture. We show that for Akyio test streams transmitted over 3mm long link wires, the power consumption can be reduced by as much as 20% at the cost of an acceptable degradation in average peak signal to noise ratio (PSNR) with UEP. 
500 |a Electronic resource. 
650 4 |a Major Electrical Engineering. 
653 |a Communication Reliability 
653 |a Crosstalk 
653 |a Latency 
653 |a Asynchronous bypass 
653 |a NoC 
653 |a Synchronization 
653 |a Skew 
700 1 |a Choi, Seong Gwan,  |e thesis advisor. 
856 4 0 |u http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10080  |z Link to OAK Trust copy  |t 0 
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952 f f |a Texas A&M University  |b College Station  |c Electronic Resources  |d Available Online  |t 0  |e 2011 Thesis 1969.1/ETD-TAMU-2011-08-10080  |h Other scheme 
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