Analytical layer planning for nanometer vlsi designs /

Algorithms for the scaling toward nanometer VLSI physical synthesis /
by: Sze, Chin Ngai, 1977-
Published: (2007)

Layout optimization in ultra deep submicron VLSI design /
by: Wu, Di, 1976-
Published: (2006)

Voltage and Timing Adaptation for Variation and Aging Tolerance in Nanometer VLSI Circuits /
by: Shim, Kyu-Nam
Published: (2013)

Analysis and optimization of VLSI Clock Distribution Networks for skew variability reduction /
by: Rajaram, Anand Kumar, 1981-
Published: (2004)

Design for manufacturing (DFM) in submicron VLSI design /
by: Cao, Ke
Published: (2010)

An improved lagrangian relaxation method for VLSI combinational circuit optimization /
by: Huang, Yi-Le
Published: (2012)

Algorithms for VLSI circuit optimization and GPU-based parallelization /
by: Liu, Yifang
Published: (2010)

Current-mode VLSI analog filters : design and applications /
by: Mohan, P. V. Ananda, 1949-
Published: (2003)

Single-event effect test report Texas Instruments DS25BR100 LVDS buffer /
by: Wilcox, Ted, et al.
Published: (2021)

Quantitative thin layer chromatography /
by: Touchstone, Joseph C.
Published: (1973)

Conservation buffers : design guidelines for buffers, corridors, and greenways /
by: Bentrup, Gary
Published: (2008)

Conservation buffers : design guidelines for buffers, corridors, and greenways /
by: Bentrup, Gary
Published: (2008)

Quantitative thin-layer chromatography and its industrial applications /
Published: (1987)

Buffer states : power policies, foreign policies and concepts /
by: Tʻurmaniże, Tʻornike
Published: (2009)

Minimizing and exploiting leakage in VLSI /
by: Jayakumar, Nikhil
Published: (2010)

Case studies on lithography-friendly vlsi circuit layout /
by: Shah, Pratik Jitendra
Published: (2010)

Parallel Simulation for VLSI Power Grid /
by: Zhang, Le
Published: (2015)

The electrical double layer /
by: Sparnaay, M. J. (Marcus Johannes)
Published: (1972)

Physical layer model design for wireless networks /
by: Yu, Yi
Published: (2010)

A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects /
by: Kansal, Rohan
Published: (2013)

Low power low-density parity-checking (LDPC) codes decoder design using dynamic voltage and frequency scaling /
by: Wang, Weihuang
Published: (2010)

Isoelectric focusing : theory, methodology, and applications /
by: Righetti, P. G.
Published: (1983)

The discovery and characterization of transposable elements : the collected papers of Barbara McClintock.
by: McClintock, Barbara, 1902-1992
Published: (1987)

Isoelectric focusing : theory, methodology, and applications /
by: Righetti, P. G.
Published: (1983)

Buffer solutions /
by: Beynon, R. J. (Robert J.)
Published: (1996)

Fast interconnect optimization /
by: Li, Zhuo, 1980-
Published: (2006)

Design and synthesis of novel isoelectric buffers /
by: Lalwani, Sanjiv Kumar Shankerdass, 1977-
Published: (2006)

Polynomial Approximation Of Circuit Responses For Optimal Design Of VLSI Circuits.
by: Khammash, Mustafa Hani
Published: (1986)

Retroviral insertion and oncogene activation /
Published: (1991)

In-between border spaces in the levant /
Published: (2021)

Buffer states in world politics /
Published: (1986)

Timing synchronization at the relay node in physical layer network coding /
by: Basireddy, Ashish
Published: (2012)

Trade shocks in developing countries /
Published: (1999)

Analog VLSI design automation /
by: Balkr, Sina
Published: (2003)

STT-MRAM based NoC buffer design /
by: Vikram Kulkarni, Nikhil
Published: (2012)

Layer-by-Layer Assembled Smectite-Polymer Nanocomposite Film for Rapid Detection of Low-Concentration Aflatoxins /
by: Hu, He
Published: (2013)