Analytical layer planning for nanometer vlsi designs /

Bibliographic Details
Main Author: Zhang, Qiyou
Other Authors: Hu, Jiang (Thesis advisor)
Format: Thesis eBook
Language:English
Published: [College Station, Tex.] : [Texas A&M University], [2012]
Subjects:
Online Access:Link to OAK Trust copy

MARC

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100 1 |a Zhang, Qiyou. 
245 1 0 |a Analytical layer planning for nanometer vlsi designs /  |c by Chi-Yu Chang. 
264 1 |a [College Station, Tex.] :  |b [Texas A&M University],  |c [2012] 
300 |a 1 online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
500 |a "Major Subject: Electrical Engineering" 
588 |a Description from author supplied metadata (automated record created 2012-10-22 13:24:58). 
502 |b Master of Science  |c Texas A&M University  |d 2012  |o http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11584 
504 |a Includes bibliographical references. 
516 |a Text (Thesis) 
520 3 |a In this thesis, we proposed an intermediate sub-process between placement and routing stage in physical design. The algorithm is for generating layer guidance for post-placement optimization technique especially buffer insertion. This issue becomes critical in nowadays VLSI chip design due to the factor of timing, congestion, and increasingly non-uniform parasitic among different metal layers. Besides, as a step before routing, this layer planning algorithm accounts for routability by considering minimized overlap area between different nets. Moreover, layer directive information which is a crucial concern in industrial design is also considered in the algorithm. The core problem is formulated as nonlinear programming problem which is composed of objective function and constraints. The problem is further solved by conjugate gradient method. The whole algorithm is implemented by C++ under Linux operating system and tested on ISPD2008 Global Routing Contest Benchmarks. The experiment results are shown in the end of this thesis and confirm the effectiveness of our approach especially in routability aspect. 
500 |a Electronic resource. 
650 4 |a Major Electrical Engineering. 
653 |a physical design 
653 |a analytical 
653 |a layer planning 
653 |a VLSI 
653 |a buffer insertion 
653 |a routability 
700 1 |a Hu, Jiang,  |e thesis advisor. 
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