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| LEADER |
00000cam a2200000Ka 4500 |
| 001 |
in00002783748 |
| 005 |
20150922144944.0 |
| 006 |
m fo d |
| 007 |
cr unu|||||||| |
| 008 |
121120s2012 txu obm 000 0 eng d |
| 035 |
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|a (OCoLC)ocn818755200
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| 035 |
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|a (OCoLC)818755200
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| 035 |
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|a (TxCM)http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684
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| 040 |
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|a TXA
|c TXA
|d TXA
|d UtOrBLW
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| 049 |
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|a TXAM
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| 099 |
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|a 2012
|a Thesis
|a 1969.1/ETD-TAMU-2012-08-11684
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| 100 |
1 |
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|a Vikram Kulkarni, Nikhil.
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| 245 |
1 |
0 |
|a STT-MRAM based NoC buffer design /
|c by Nikhil Vikram Kulkarni.
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| 264 |
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1 |
|a [College Station, Tex.] :
|b [Texas A&M University],
|c [2012]
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| 300 |
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|a 1 online resource.
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| 336 |
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 500 |
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|a "Major Subject: Computer Engineering"
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| 588 |
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|a Description from author supplied metadata (automated record created 2012-10-22 13:24:58).
|
| 502 |
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|b Master of Science
|c Texas A&M University
|d 2012
|o http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684
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| 504 |
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|a Includes bibliographical references.
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| 516 |
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|a Text (Thesis)
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| 520 |
3 |
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|a As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory - STT MRAM (Spin-Torque Transfer Magnetic RAM) which provides substantial power and area savings, near zero leakage power, and displays higher memory density compared to conventional SRAM. But STT-MRAM suffers from inherit drawbacks like multi cycle write latency and high write power consumption. So, these problem have to addressed in order to have an efficient design to incorporate STT-MRAM for NoC input buffer instead of traditional SRAM based input buffer design. Motivated by short intra-router latency, previously proposed write latency reduction technique is explored by sacrificing retention time and a hybrid design of input buffers using both SRAM and STT-MRAM to "hide" the long write latency efficiently is proposed. Considering that simple data migration in the hybrid buffer consumes more dynamic power compared to SRAM, a lazy migration scheme that reduces the dynamic power consumption of the hybrid buffer is also proposed.
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| 500 |
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|a Electronic resource.
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| 650 |
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4 |
|a Major Computer Engineering.
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| 653 |
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|a STT-MRAM
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| 653 |
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|a Noc
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| 653 |
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|a Buffer
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| 700 |
1 |
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|a Kim, Eun Jung,
|e thesis advisor.
|
| 856 |
4 |
0 |
|u http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684
|z Link to OAK Trust copy
|t 0
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| 948 |
|
|
|a cataloged
|b h
|c 2012/11/20
|d o
|e jwilkinson
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| 994 |
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|a C0
|b TXA
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| 999 |
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|a MARS
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| 999 |
f |
f |
|s 019f80d7-d51d-32b9-b27f-833f20c31094
|i 756f030e-a350-3c90-81ed-47132e2bdef8
|t 0
|
| 952 |
f |
f |
|a Texas A&M University
|b College Station
|c Electronic Resources
|d Available Online
|t 0
|e 2012 Thesis 1969.1/ETD-TAMU-2012-08-11684
|h Other scheme
|
| 998 |
f |
f |
|a 2012 Thesis 1969.1/ETD-TAMU-2012-08-11684
|t 0
|l Available Online
|