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00000cam a2200000Ka 4500 |
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20150922123911.0 |
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m f d |
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cr unu|||||||| |
| 008 |
121012s2012 txu obm 000 0 eng d |
| 035 |
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|a (OCoLC)ocn812658249
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| 035 |
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|a (OCoLC)812658249
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| 035 |
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|a (TxCM)http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10266
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| 040 |
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|a TXA
|c TXA
|d UtOrBLW
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| 049 |
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|a TXAM
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|a 2011
|a Thesis
|a 1969.1/ETD-TAMU-2011-12-10266
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|a Lahiri, Shayak.
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|a Pseudofunctional delay tests for high quality small delay defect testing /
|c by Shayak Lahiri.
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| 264 |
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|a [College Station, Tex.] :
|b [Texas A&M University],
|c [2012]
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|a 1 online resource.
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| 336 |
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 500 |
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|a "Major Subject: Computer Engineering"
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|a Description from author supplied metadata (automated record created 2012-07-26 09:07:26).
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| 502 |
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|b Master of Science
|c Texas A&M University
|d 2011
|o http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10266
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|a Includes bibliographical references.
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|a Text (Thesis)
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|a Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time.
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|a Electronic resource.
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|a Major Computer Engineering.
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|a test generation
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|a path delay test
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|a small delay defect
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|a pseudo functional test
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|a delay test
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|a power supply noise
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| 653 |
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|a dynamic compaction
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| 653 |
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|a ATPG
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| 700 |
1 |
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|a Walker, Duncan Moore Henry,
|e thesis advisor.
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| 856 |
4 |
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|u http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10266
|z Link to OAK Trust copy
|t 0
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| 994 |
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|a C0
|b TXA
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| 948 |
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|a cataloged
|b h
|c 2012/10/12
|d o
|e jho
|f 3:04:23 pm
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| 999 |
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|a MARS
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| 999 |
f |
f |
|s 729929e7-4078-307c-a145-267f370eb7ff
|i 12ca2a66-57d9-30eb-8cf1-01f6778ad093
|t 0
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| 952 |
f |
f |
|a Texas A&M University
|b College Station
|c Electronic Resources
|d Available Online
|t 0
|e 2011 Thesis 1969.1/ETD-TAMU-2011-12-10266
|h Other scheme
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| 998 |
f |
f |
|a 2011 Thesis 1969.1/ETD-TAMU-2011-12-10266
|t 0
|l Available Online
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