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Timing aware partitioning for multi-fpga based logic simulation using top-down selective flattening.

Bibliographic Details
Main Author:	Poothamkurissi Swaminathan, Subramanian
Other Authors:	Khatri, Sunil P. (Thesis advisor)
Format:	Thesis eBook
Language:	English
Published:	[College Station, Tex.] : [Texas A&M University], [2012]
Subjects:	Major Computer Engineering. FPGA Partitioning Selective Hierarchy Flattening FPGA based Acceleration
Online Access:	Link to OAK Trust copy

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