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121112s2012 txu obm 000 0 eng d |
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|a (OCoLC)ocn817224699
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|a (OCoLC)817224699
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|a (TxCM)http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11789
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|a TXA
|c TXA
|d UtOrBLW
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|a TXAM
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|a 2012
|a Thesis
|a 1969.1/ETD-TAMU-2012-08-11789
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|a Poothamkurissi Swaminathan, Subramanian.
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|a Timing aware partitioning for multi-fpga based logic simulation using top-down selective flattening.
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|a [College Station, Tex.] :
|b [Texas A&M University],
|c [2012]
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|a 1 online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
|2 rdacarrier
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|a "Major Subject: Computer Engineering"
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|a Description from author supplied metadata (automated record created 2012-10-22 13:24:58).
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| 502 |
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|b Master of Science
|c Texas A&M University
|d 2012
|o http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11789
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|a Includes bibliographical references.
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|a Text (Thesis)
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|a In order to accelerate logic simulation, it is highly beneficial to simulate the circuit design on FPGA hardware. However, limited hardware resources on FPGAs prevent large designs from being implemented on a single FPGA. Hence there is a need to partition the design and simulate it on a multi-FPGA platform. In contrast to existing FPGA-based post-synthesis partitioning approaches which first completely flatten the circuit and then possibly perform bottom-up clustering, we perform a selective top-down flattening and thereby avoid the potential netlist blowup. This also allows us to preserve the design hierarchy to guide the partitioning and to make subsequent debugging easier. Our approach analyzes the hierarchical design and selectively flattens instances using two metrics based on slack. The resulting partially flattened netlist is converted to a hypergraph, partitioned using a public domain partitioner (hMetis), and reconverted back to a plurality of FPGA netlists, one for each FPGA of the FPGA-based accelerated logic simulation platform. We compare our approach with a partitioning approach that operates on a completely flattened netlist. Static timing analysis was performed for both approaches, and over 15 examples from the OpenCores project, our approach yields a 52% logic simulation speedup and about 0.74x runtime for the entire flow, compared to the completely flat approach. The entire tool chain of our approach is automated in an end-to-end flow from hierarchy extraction, selective flattening, partitioning, and netlist reconstruction. Compared to an existing method which also performs slack-based partitioning of a hierarchical netlist, we obtain a 35% simulation speedup.
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|a Electronic resource.
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|a Major Computer Engineering.
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|a FPGA Partitioning
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|a Selective Hierarchy Flattening
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| 653 |
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|a FPGA based Acceleration
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|a Khatri, Sunil P.,
|e thesis advisor.
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|u http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11789
|z Link to OAK Trust copy
|t 0
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|a cataloged
|b h
|c 2012/11/12
|d o
|e jstorlie
|f 2:26:36 pm
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|a C0
|b TXA
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|a MARS
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|i 8ff9e061-cccd-30e5-ab30-388a9747037b
|t 0
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| 952 |
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|a Texas A&M University
|b College Station
|c Electronic Resources
|s www_evans
|d Available Online
|t 0
|e 2012 Thesis 1969.1/ETD-TAMU-2012-08-11789
|h Other scheme
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| 998 |
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f |
|a 2012 Thesis 1969.1/ETD-TAMU-2012-08-11789
|t 0
|l Available Online
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