APA (7th ed.) Citation

Poothamkurissi Swaminathan, S., & Khatri, S. P. (2012). Timing aware partitioning for multi-fpga based logic simulation using top-down selective flattening. [Texas A&M University].

Chicago Style (17th ed.) Citation

Poothamkurissi Swaminathan, Subramanian, and Sunil P. Khatri. Timing Aware Partitioning for Multi-fpga Based Logic Simulation Using Top-down Selective Flattening. [College Station, Tex.]: [Texas A&M University], 2012.

MLA (9th ed.) Citation

Poothamkurissi Swaminathan, Subramanian, and Sunil P. Khatri. Timing Aware Partitioning for Multi-fpga Based Logic Simulation Using Top-down Selective Flattening. [Texas A&M University], 2012.