APA (7th ed.) Citation

Deshpande, H., & Choi, S. G. (2012). Multipath router architectures to reduce latency in Network-on-Chips. [Texas A&M University].

Chicago Style (17th ed.) Citation

Deshpande, Hrishikesh, and Seong Gwan Choi. Multipath Router Architectures to Reduce Latency in Network-on-Chips. [College Station, Tex.]: [Texas A&M University], 2012.

MLA (9th ed.) Citation

Deshpande, Hrishikesh, and Seong Gwan Choi. Multipath Router Architectures to Reduce Latency in Network-on-Chips. [Texas A&M University], 2012.