rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Parallel VLSI circuit analysis and optimization
  name:
    name part: Ye, Xiaoji.
    role:
      role term: creator
  name:
    name part: Li, Peng
    role:
      role term: thesis advisor.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: txu
    date issued: 2012
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource.
  abstract: The prevalence of multi-core processors in recent years has introduced new opportunities and challenges to Electronic Design Automation (EDA) research and development. In this dissertation, a few parallel Very Large Scale Integration (VLSI) circuit analysis and optimization methods which utilize the multi-core computing platform to tackle some of the most difficult contemporary Computer-Aided Design (CAD) problems are presented. The first CAD application that is addressed in this dissertation is analyzing and optimizing mesh-based clock distribution network. Mesh-based clock distribution network (also known as clock mesh) is used in high-performance microprocessor designs as a reliable way of distributing clock signals to the entire chip. The second CAD application addressed in this dissertation is the Simulation Program with Integrated Circuit Emphasis (SPICE) like circuit simulation. SPICE simulation is often regarded as the bottleneck of the design flow. Recently, parallel circuit simulation has attracted a lot of attention. The first part of the dissertation discusses circuit analysis techniques. First, a combination of clock network specific model order reduction algorithm and a port sliding scheme is presented to tackle the challenges in analyzing large clock meshes with a large number of clock drivers. Our techniques run much faster than the standard SPICE simulation and existing model order reduction techniques. They also provide a basis for the clock mesh optimization. Then, a hierarchical multi-algorithm parallel circuit simulation (HMAPS) framework is presented as an novel technique of parallel circuit simulation. The inter-algorithm parallelism approach in HMAPS is completely different from the existing intra-algorithm parallel circuit simulation techniques and achieves superlinear speedup in practice. The second part of the dissertation talks about parallel circuit optimization. A modified asynchronous parallel pattern search (APPS) based method which u…
  note: by Xiaoji Ye.
  note: "Major Subject: Computer Engineering"
  note: Electronic resource.
  note: Doctor of Philosophy Texas A&M University 2010 http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8597
  note: Includes bibliographical references.
  note: Text (Dissertation)
  subject:
    topic: Major computer engineering
  subject:
    topic: Parallel computing
  subject:
    topic: circuit optimization
  subject:
    topic: circuit simulation
  identifier: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8597
  record info:
    record content source: TXA
    record creation date: 120321
    record change date: 20151202151900.0
    record identifier: in00002747109