rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    non sort: An
    title: improved lagrangian relaxation method for VLSI combinational circuit optimization
  name:
    name part: Huang, Yi-Le.
    role:
      role term: creator
  name:
    name part: Shi, Weiping
    role:
      role term: thesis advisor.
  name:
    name part: Hu, Jiang
    role:
      role term: thesis advisor.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: txu
    date issued: 2012
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource.
  abstract: Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common method for handling multi-objectives and proven to reach optimal solution under continuous solution space. However, it is more complex to use Lagrangian relaxation under discrete solution space. The Lagrangian dual problem is non-convex and previously a sub-gradient method was used to solve it. The sub-gradient method is a greedy approach for substituting gradient method in the deepest descent method, and has room for further improvement. In addition, Lagrangian sub-problem cannot be solved directly by mathematical approaches under discrete solution space. Here we propose a new Lagrangian relaxation-based method for simultaneous gate sizing and Vt assignment under discrete solution space. In this work, some new approaches are provided to solve the Lagrangian dual problem considering not only slack but also the relationship between Lagrangian multipliers and circuit timing. We want to solve the Lagrangian dual problem more precisely than did previous methods, such as the sub-gradient method. In addition, a table-lookup method is provided to replace mathematical approaches for solving the Lagrangian sub-problem under discrete size and Vt options. The experimental results show that our method can lead to about 50 percent and 58 percent power reduction subject to the same timing constraints compared with a Lagrangian relaxation method using sub-gradient method and a state-of-the-art previous work. These two methods are implemented by us for comparison. Our method also results in better circuit timing subject to tight timing constraints.
  note: by Yi-Le Huang.
  note: "Major Subject: Electrical Engineering"
  note: Electronic resource.
  note: Master of Science Texas A&M University 2010 http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8684
  note: Includes bibliographical references.
  note: Text (Thesis)
  subject:
    topic: Major electrical engineering
  subject:
    topic: VLSI
  subject:
    topic: low power
  subject:
    topic: circuit optimization
  subject:
    topic: gate sizing
  identifier: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8684
  record info:
    record content source: TXA
    record creation date: 120307
    record change date: 20151202151704.0
    record identifier: in00002746831