Palaniappan, A., & Palermo, S. (2012). Modeling, optimization and power efficiency comparison of high-speed inter-chip electrical and optical interconnect architectures in nanometer CMOS technologies. [Texas A&M University].
Chicago Style (17th ed.) CitationPalaniappan, Arun, and Samuel Palermo. Modeling, Optimization and Power Efficiency Comparison of High-speed Inter-chip Electrical and Optical Interconnect Architectures in Nanometer CMOS Technologies. [College Station, Tex.]: [Texas A&M University], 2012.
MLA (9th ed.) CitationPalaniappan, Arun, and Samuel Palermo. Modeling, Optimization and Power Efficiency Comparison of High-speed Inter-chip Electrical and Optical Interconnect Architectures in Nanometer CMOS Technologies. [Texas A&M University], 2012.
Warning: These citations may not always be 100% accurate.