rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: High quality compact delay test generation
  name:
    name part: Wang, Zheng.
    role:
      role term: creator
  name:
    name part: Walker, Duncan Moore Henry
    role:
      role term: thesis advisor.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: txu
    date issued: 2011
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource.
  abstract: Delay testing is used to detect timing defects and ensure that a circuit meets its timing specifications. The growing need for delay testing is a result of the advances in deep submicron (DSM) semiconductor technology and the increase in clock frequency. Small delay defects that previously were benign now produce delay faults, due to reduced timing margins. This research focuses on the development of new test methods for small delay defects, within the limits of affordable test generation cost and pattern count. First, a new dynamic compaction algorithm has been proposed to generate compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting necessary assignments together during test generation. Second, to make this dynamic compaction approach practical for industrial use, a recursive learning algorithm has been implemented to identify more necessary assignments for each path, so that the path-to-test-pattern matching using necessary assignments is more accurate. Third, a realistic low cost fault coverage metric targeting both global and local delay faults has been developed. The metric suggests the test strategy of generating a different number of longest paths for each line in the circuit while maintaining high fault coverage. The number of paths and type of test depends on the timing slack of the paths under this metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits show that the pattern count of KLPG can be significantly reduced using the proposed methods. The pattern count is comparable to that of transition fault test, while achieving higher test quality. Finally, the proposed ATPG methodology has been applied to an industrial quad-core microprocessor. FMAX testing has been done on many devices and silicon data has shown the benefit of KLPG test.
  note: by Zheng Wang.
  note: "Major Subject: Computer Engineering"
  note: Title from author supplied metadata (automated record created 2011-08-09 15:09:44).
  note: Electronic resource.
  note: Doctor of Philosophy Texas A&M University 2010 http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7976
  note: Includes bibliographical references.
  note: Text (Dissertation)
  subject:
    topic: Major computer engineering
  subject:
    topic: Delay Test
  subject:
    topic: ATPG
  subject:
    topic: Test Compaction
  identifier: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7976
  record info:
    record content source: TXA
    record creation date: 110816
    record change date: 20151202142256.0
    record identifier: in00002705855