APA (7th ed.) Citation

Jespers, P. G. (2010). The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits: The semi-empirical and compact model approaches. Springer. https://doi.org/10.1007/978-0-387-47101-3

Chicago Style (17th ed.) Citation

Jespers, Paul G. The Gm/ID Design Methodology, a Sizing Tool for Low-voltage Analog CMOS Circuits: The Semi-empirical and Compact Model Approaches. Dordrecht ; London ; New York: Springer, 2010. https://doi.org/10.1007/978-0-387-47101-3.

MLA (9th ed.) Citation

Jespers, Paul G. The Gm/ID Design Methodology, a Sizing Tool for Low-voltage Analog CMOS Circuits: The Semi-empirical and Compact Model Approaches. Springer, 2010. https://doi.org/10.1007/978-0-387-47101-3.