rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy
  name:
    name part: Chang, Sanghoan.
    role:
      role term: creator
  name:
    name part: Choi, Seong Gwan
    role:
      role term: thesis advisor.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: txu
    date issued: 2010
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: remote
    extent: 1 online resource.
  abstract: The operating clock frequency is determined by the longest signal propagation delay, setup/hold time, and timing margin. These are becoming less predictable with the increasing design complexity and process miniaturization. The difficult challenge is then to ensure that a device operating at its clock frequency is error-free with quantifiable assurance. Effort at device-level engineering will not suffice for these circuits exhibiting wide process variation and heightened sensitivities to operating condition stress. Logic-level redress of this issue is a necessity and we propose a design-level remedy for this timing-uncertainty problem. The aim of the design and analysis approaches presented in this dissertation is to provide framework, SABRE, wherein an increased operating clock frequency can be achieved. The approach is a combination of analytical modeling, experimental analysis, hardware /time-redundancy design, exception handling and recovery techniques. Our proposed design replicates only a necessary part of the original circuit to avoid high hardware overhead as in triple-modular-redundancy (TMR). The timing-critical combinational circuit is path-wise partitioned into two sections. The combinational circuits associated with long paths are laid out without any intrusion except for the fan-out connections from the first section of the circuit to a replicated second section of the combinational circuit. Thus only the second section of the circuit is replicated. The signals fanning out from the first section are latches, and thus are far shorter than the paths spanning the entire combinational circuit. The replicated circuit is timed at a subsequent clock cycle to ascertain relaxed timing paths. This insures that the likelihood of mistiming due to stress or process variation is eliminated. During the subsequent clock cycle, the outcome of the two logically identical, yet time-interleaved, circuit outputs are compared to detect faults. When a fault is detected, the …
  note: by Sanghoan Chang.
  note: "Major Subject: Computer Engineering"
  note: Title from author supplied metadata (automated record created 2010-03-12 12:08:51).
  note: Electronic resource.
  note: Doctor of Philosophy Texas A&M University 2007 http://hdl.handle.net/1969.1/ETD-TAMU-1270
  note: Includes bibliographical references.
  note: Text (Dissertation)
  subject:
    topic: Major computer engineering
  subject:
    topic: FMAX
  subject:
    topic: Timing
  subject:
    topic: Fault tolerant
  subject:
    topic: Delay
  identifier: http://hdl.handle.net/1969.1/ETD-TAMU-1270
  record info:
    record content source: TXA
    record creation date: 100429
    record change date: 20151201150209.0
    record identifier: in00002587207