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100428s2010 txu sbm 000 0 eng d |
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|a (OCoLC)ocn609886224
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|a (OCoLC)609886224
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|a (TxCM)http://hdl.handle.net/1969.1/ETD-TAMU-1497
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|a TXA
|c TXA
|d UtOrBLW
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|a TXAM
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|a 2007
|a Dissertation
|a 1969.1/ETD-TAMU-1497
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|a Tong, Haitao.
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|a Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems /
|c by Haitao Tong.
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|a [College Station, Tex.] :
|b [Texas A&M University],
|c [2010]
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|a 1 online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
|2 rdacarrier
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|a "Major Subject: Electrical Engineering"
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|a Title from author supplied metadata (automated record created 2010-03-12 12:08:51).
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|b Doctor of Philosophy
|c Texas A&M University
|d 2007
|o http://hdl.handle.net/1969.1/ETD-TAMU-1497
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|a Includes bibliographical references.
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|a Text (Dissertation)
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|a Ultra-wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer-based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase-locked loop (PLL)-based synthesizers. Harmonic cancelation technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5-GHz CSD-QVCO in 0.18 um CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is -120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD-QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Implemented with three stages in 0.18 um CMOS technology, the ILFD draws 3-mA current from a 1.8-V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range.
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|a Electronic resource.
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|a Major electrical engineering.
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|a injection-locking frequency divider
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|a harmonic cancellation
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|a UWB
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|a qudrature signal generation
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|a frequency synthesizer
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|a Karșilayan, Aydin İlker,
|e thesis advisor.
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|u http://hdl.handle.net/1969.1/ETD-TAMU-1497
|z Link to OAK Trust copy
|t 0
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| 948 |
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|a cataloged
|b h
|c 2010/4/28
|d c
|e jgreene
|f 12:43:59 pm
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|a C0
|b TXA
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|a MARS
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|t 0
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| 952 |
f |
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|a Texas A&M University
|b College Station
|c Electronic Resources
|d Available Online
|t 0
|e 2007 Dissertation 1969.1/ETD-TAMU-1497
|h Other scheme
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| 998 |
f |
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|a 2007 Dissertation 1969.1/ETD-TAMU-1497
|t 0
|l Available Online
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