rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Fault tolerant computer architecture
  title info:
    title: Synthesis digital library of engineering and computer science
  name:
    name part: Sorin, Daniel J.
    role:
      role term: creator
  type of resource: text
  genre: abstract or summary
  genre: Electronic books.
  origin info:
    place:
      place term: cau
    date issued: 2009
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    reformatting quality: access
    form: remote
    extent: 1 electronic text (xii, 103 pages : illustrations) : digital file.
  abstract: For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art--over approximately the past 10 years--in academia and industry.
  table of contents: Introduction -- Goals of this book -- Faults, errors, and failures -- Masking -- Duration of faults and errors -- Underlying physical phenomena -- Trends leading to increased fault rates -- Smaller devices and hotter chips -- More devices per processor -- More complicated designs -- Error models -- Error type -- Error duration -- Number of simultaneous errors -- Fault tolerance metrics -- Availability -- Reliability -- Mean time to failure -- Mean time between failures -- Failures in time -- Architectural vulnerability factor -- The rest of this book -- References -- Error detection -- General concepts -- Physical redundancy -- Temporal redundancy -- Information redundancy -- The end-to-end argument -- Microprocessor cores -- Functional units -- Register files -- Tightly lockstepped redundant cores -- Redundant multithreading without lockstepping -- Dynamic verification of invariants -- High-level anomaly detection -- Using software to detect hardware errors -- Error detection tailored to specific fault models -- Caches and memory -- Error code implementation -- Beyond EDCs -- Detecting errors in content addressable memories -- Detecting errors in addressing -- Multiprocessor memory systems -- Dynamic verification of cache coherence -- Dynamic verification of memory consistency -- Interconnection networks -- Conclusions -- References -- Error recovery -- General concepts -- Forward error recovery -- Backward error recovery -- Comparing the performance of FER and BER -- Microprocessor cores -- FER for cores -- BER for cores -- Single-core memory systems -- FER for caches and memory -- BER for caches and memory -- Issues unique to multiprocessors -- What state to save for the recovery point -- Which algorithm to use for saving the recovery point -- Where to save the recovery point -- How to restore the recovery point state -- Software-implemented BER -- Conclusions -- References -- Diagnosis -- General concepts -- The benefits of diagnosis -- System model implications…
  target audience: specialized
  note: Daniel J. Sorin.
  note: Electronic resource.
  note: Part of: Synthesis digital library of engineering and computer science.
  note: Series from website.
  note: Title from PDF title page (viewed on June 4, 2009).
  note: Compendex
  note: Google book search
  note: Google scholar
  note: INSPEC
  note: Also available in print.
  note: Mode of access: World Wide Web.
  note: System requirements: Adobe Acrobat reader.
  note: Includes bibliographical references.
  subject:
    topic: Computer architecture
  subject:
    topic: Fault-tolerant computing
  subject:
    topic: Self-stabilization (Computer science)
  classification: QA76.9.F38 S674 2009
  classification: 004.2
  related item:
    note: Compendex
  related item:
    note: Google book search
  related item:
    note: Google scholar
  related item:
    note: INSPEC
  related item:
    title info:
      title: Synthesis lectures in computer architecture (Online) ; #5
  identifier: 1598299549 (electronic bk.)
  identifier: 9781598299540 (electronic bk.)
  identifier: 9781598299533 (pbk.)
  identifier: http://proxy.library.tamu.edu/login
  record info:
    record content source: CaBNvSL
    record creation date: 090604
    record change date: 20210727090313.0
    record identifier: in00002544887