rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: SystemVerilog for verification
    sub title: a guide to learning the testbench language features
  name:
    name part: Spear, Chris.
    role:
      role term: creator
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  genre: bibliography
  genre: Electronic books.
  origin info:
    place:
      place term: nyu
    date issued: 2006
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: remote
    extent: xxxiv, 301 pages : illustrations ; 25 cm.
  note: Chris Spear.
  note: Electronic resource.
  note: Electronic reproduction. New York : Springer, 2008. Mode of access: World Wide Web. System requirements: Web browser. Title from title screen (viewed on Jan. 30, 2008). Access may be restricted to users at subscribing institutions.
  note: Includes bibliographical references (pages [295]-296) and index.
  subject:
    topic: Integrated circuits
    topic: Verification
  subject:
    topic: Verilog (Computer hardware description language)
  subject:
    topic: Circuits intégrés
    topic: Vérification
  subject:
    topic: Verilog (Langage de description de matériel informatique)
  classification: TK7885.7 .S67 2006eb
  classification: 621.39/2
  related item:
    identifier: (DLC) 2006926262
    identifier: (OCoLC)71200163
  identifier: 0387270388
  identifier: 9780387270388
  identifier: 978-0-387-27036-4 Springer
  identifier: http://proxy.library.tamu.edu/login
  record info:
    record content source: GW5XE
    record creation date: 080226
    record change date: 20210817091357.0
    record identifier: in00002473261