ASIC and FPGA verification : a guide to component modeling /
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
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| Format: | eBook |
| Language: | English |
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San Francisco, Calif. :
Morgan Kaufmann,
2004.
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| Series: | Morgan Kaufmann series in systems on silicon.
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| Subjects: | |
| Online Access: | Connect to the full text of this electronic book |
| Summary: | Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification. |
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| Item Description: | Includes index. Electronic resource. |
| Physical Description: | xx, 316 pages : illustrations ; 24 cm. |
| ISBN: | 9780125105811 0125105819 |