http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.
Electronic reproduction. Amsterdam : Elsevier Science & Technology, 2007. Mode of access: World Wide Web. System requirements: Web browser. Title from title screen (viewed on Aug. 2, 2007). Access may be restricted to users at subscribing institutions.
Includes bibliographical references and index.
Morgan Kaufmann series in systems on silicon
132281:132389 Elsevier Science & Technology