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VLSI test principles and architectures : design for testability /

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This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of indu...

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Bibliographic Details
Other Authors: Wang, Laung-Terng, Wu, Cheng-Wen, EE Ph. D., Wen, Xiaoqing
Format: eBook
Language:English
Published: Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, [2006]
Series:Morgan Kaufmann series in systems on silicon.
Subjects:
Integrated circuits > Very large scale integration > Testing.
Integrated circuits > Very large scale integration > Design.
Circuits intégrés à très grande échelle > Essais.
Circuits intégrés à très grande échelle > Conception et construction.
Electronic books.
Online Access:Connect to the full text of this electronic book
Table of contents
Publisher description
Description
Summary:This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
Item Description:Electronic resource.
Physical Description:xxx, 777 pages : illustrations ; 25 cm.
Bibliography:Includes bibliographical references and index.
ISBN:9780123705976
0123705975