rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Verification methodology manual for SystemVerilog
  name:
    name part: Bergeron, Janick.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: nyu
    date issued: 2006
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    extent: xvii, 503 pages : illustrations ; 24 cm.
  note: by Janick Bergeron [and others].
  note: Includes bibliographical references and index.
  subject:
    topic: Verilog (Computer hardware description language)
  subject:
    topic: Integrated circuits
    topic: Verification
  classification: TK7885.7 .V44 2006
  classification: 621.39/2
  identifier: 0387255389 (alk. paper)
  identifier: 0387255567 (e-book)
  identifier: 2005051724
  record info:
    record content source: DLC
    record creation date: 050816
    record change date: 20151103050817.0
    record identifier: in00002104433