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Logic-timing simulation and the degradation delay model /

Bibliographic Details
Main Author:	Bellido, Manuel J., 1964-
Other Authors:	Juan, Jorge, Valencia, Manuel
Format:	Book
Language:	English
Published:	London ; Hackensack, NJ : Imperial College Press, [2006]
Subjects:	Timing circuits. Integrated circuits > Very large scale integration. Metal oxide semiconductors, Complementary.

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