Cover Image

Logic-timing simulation and the degradation delay model /

Bibliographic Details
Main Author: Bellido, Manuel J., 1964-
Other Authors: Juan, Jorge, Valencia, Manuel
Format: Book
Language:English
Published: London ; Hackensack, NJ : Imperial College Press, [2006]
Subjects:
Timing circuits.
Integrated circuits > Very large scale integration.
Metal oxide semiconductors, Complementary.
Description
Physical Description:xvii, 267 pages : illustrations ; 24 cm.
Bibliography:Includes bibliographical references and index.
ISBN:1860945899 (hb)