rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    non sort: An
    title: energy efficient TCAM enhanced cache architecture
  name:
    name part: Surprise, Jason Mathew, 1979-
    role:
      role term: creator
  name:
    name part: Mahapatra, Rabi N.
    role:
      role term: thesis advisor.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: txu
    date issued: 2005
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: remote
  abstract: Microprocessors are used in a variety of systems ranging from high-performance super computers running scientific applications to battery powered cell phones performing realtime tasks. Due to the large disparity between processor clock speed and main memory access time, most modern processors include several caches, which consume more than half of the total chip area and power budget. As the performance gap between processors andmemory has increased, the trend has been to increase the size of the on-chip caches. However, increasing the cache size also increases its access time and energy consumptions. This growing power dissipation problem is making traditional cooling and packaging techniques less effective thus requiring cache designers to focus more on architectural level energy efficiency than performance alone. The goal of this thesis is to propose a new cache architecture and to evaluate its efficiency in terms of miss rate, system performance, energy consumption, and area overhead. The proposed architecture employs the use of a few Ternary-CAM (TCAM) cells in the tag array to enable dynamic compression of tag entries containing contiguous values. By dynamically compressing tag entries, the number of entries in the tag array can be reduced by 2[superscript]N, where N is the number of tag bits that can be compressed. The architecture described in this thesis is applicable to any cache structure that uses Content Addressable Memory (CAM) cells to store tag bits. To evaluate the effectiveness of the TCAM Enhanced Cache Architecture for a wide scope of applications, two case studies were performed - the L2 Data-TLB (DTLB) of a high-performance processor and the L1 instruction and data caches of a low-power embedded processor. Results indicate that a L2 DTLB implementing 3-bit tag compression can achieve 93% of the performance of a conventional L2 DTLB of the same size while reducing the on-chip energy consumption by 74% and the total area by 50%. Similarly, an emb…
  note: by Jason Mathew Surprise.
  note: "Major Subject: Computer Science"
  note: Title from author supplied metadata (automated record created on Sep. 21, 2005.)
  note: Vita.
  note: Abstract.
  note: Electronic resource.
  note: Mode of access: World Wide Web.
  note: System requirements: World Wide Web access and Adobe Acrobat Reader.
  note: M. S. Texas A&M University 2005.
  note: Includes bibliographical references.
  note: Text (Thesis).
  subject:
    topic: Major computer science
  subject:
    topic: area efficient
  subject:
    topic: compression
  subject:
    topic: low-power
  subject:
    topic: TCAM
  subject:
    topic: cache
  subject:
    topic: energy efficient
  identifier: http://hdl.handle.net/1969.1/2314
  record info:
    record content source: TXA
    record creation date: 051102
    record change date: 20151102144651.0
    record identifier: in00002091725