rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Power supply partitioning for placement of built-in current sensors for IDDQ testing
  name:
    name part: Prasad, Abhijit
    name part: 1976-
    role:
      role term: creator
  name:
    name part: Walker, Duncan Moore Henry
    role:
      role term: thesis advisor.
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: txu
    date issued: 2004
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
  abstract: IDDQ testing has been a very useful test screen for CMOS circuits. However, with each technology node the background leakage of chips is rapidly increasing. As a result it is becoming more difficult to distinguish between faulty and fault-free chips using IDDQ testing. Power supply partitioning has been proposed to increase test resolution by partitioning the power supply network, such that each partition has a relatively small defect-free IDDQ level. However, at present no practical partitioning strategy is available. The contribution of this thesis is to present a practical power supply partitioning strategy. We formulate various versions of the power supply partitioning problem that are likely to be of interest depending on the constraints of the chip design. Solutions to all the variants of the problem are presented. The basic idea behind all solutions is to abstract the power topology of the chip as a flow network. We then use flow techniques to find the min-cut of the transformed network to get solutions to our various problem formulations. Experimental results for benchmark circuits verify the feasibility of our solution methodology. The problem formulations will give complete flexibility to a test engineer to decide which factors cannot be compromised (e.g. area of BICS, test quality, etc) for a particular design and accordingly choose the appropriate problem formulation. The application of this work will be the first step in the placement of Built-In Current Sensors for IDDQ testing.
  note: by Abhijit Prasad.
  note: "Major Subject: Computer Engineering"
  note: Title from author supplied metadata (automated record created on Apr. 30, 2004.)
  note: Vita.
  note: Abstract.
  note: Electronic resource.
  note: Mode of access: World Wide Web.
  note: System requirements: World Wide Web access and Adobe Acrobat Reader.
  note: M. S. Texas A&M University 2003.
  note: Includes bibliographical references.
  note: Text (Thesis).
  subject:
    topic: Major computer engineering
  subject:
    topic: VLSI Testing
  subject:
    topic: IDDQ
  subject:
    topic: BICS
  identifier: http://hdl.handle.net/1969.1/103
  record info:
    record content source: TXA
    record creation date: 040615
    record change date: 20151026065103.0
    record identifier: in00001822998