Analysis and design of high-speed high-resolution Analog-to-Digital Converter /
A pipeline ADC (Analog-to-Digital Converter) architecture is proposed. The ADC is composed of a unique first stage and a conventional second stage. A track-hold and an operational amplifier have been proposed to be used in the ADC system. The first stage is implemented in the transistor level. It...
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| Format: | Thesis Book |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
2003.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=765867221&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | A pipeline ADC (Analog-to-Digital Converter) architecture is proposed. The ADC is composed of a unique first stage and a conventional second stage. A track-hold and an operational amplifier have been proposed to be used in the ADC system. The first stage is implemented in the transistor level. It can generate an analog residue at 10-bit accuracy level with 100MHz sampling frequency. The track-hold has a 14-bit linearity with 13MHz input frequency and 100MHz sampling frequency. The power supply is +/- 1.65V for the overall system. The circuits are designed using a 0.18 [u] m digital CMOS process and the layout is finished. Two chips have been fabricated and tested. The track-hold chip consumes 23.76mW power from a +/-1.65 V power supply. The track-hold has 11-bit resolution. The ADC chip is functional with the proposed track-hold. The results proved the research ideas. |
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| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | xii, 105 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilm Inc. |
| Bibliography: | Includes bibliographical references (leaves 102-104). |