A power aware partitioning framework for hardware-software codesign /

Existing approaches in hardware-software partitioning do not consider the maximum available system power while making the partitioning decision. Such a decision is sensitive to design efficiency when the target system is reconfigurable and supports multiple applications. Since partitioning and sched...

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Bibliographic Details
Main Author: Kappagantula, Vijay Rama Pramod, 1978-
Format: Thesis eBook
Language:English
Published: [Place of publication not identified] : [publisher not identified] ; 2003.
Subjects:
Online Access:Link to OAKTrust copy
Description
Summary:Existing approaches in hardware-software partitioning do not consider the maximum available system power while making the partitioning decision. Such a decision is sensitive to design efficiency when the target system is reconfigurable and supports multiple applications. Since partitioning and scheduling are interdependent, neglecting the available system power could result in an infeasible schedule. In this thesis, we present a power-aware partitioning technique for embedded systems that could support a set of applications. The applications specified at a task level of granularity are partitioned and scheduled such that timing and maximum available system power constraints are satisfied with minimum hardware logic.
Item Description:"Major subject: Computer Engineering".
Vita.
Physical Description:vii, 38 leaves : illustrations ; 28 cm.
Also available online.
Issued also on microfiche from Lange Micrographics.
Bibliography:Includes bibliographical references (leaves 34-37).