Low voltage high speed switched capacitor circuit design /
New methods were studied for the purpose of designing low voltage and high speed switched capacitor (SC) circuits without using the on-chip voltage bootstrapper. Auto-zeroed integrator (AZI) was proposed as the fundamental building block of low voltage SC systems. AZI has no signal dependent switche...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
2001.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=726103511&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | New methods were studied for the purpose of designing low voltage and high speed switched capacitor (SC) circuits without using the on-chip voltage bootstrapper. Auto-zeroed integrator (AZI) was proposed as the fundamental building block of low voltage SC systems. AZI has no signal dependent switches, so it can work at the low voltage with a high operating speed. Also, AZI is not sensitive to the charge injection and non-linear resistance related distortions. The low voltage two-stage fully differential opamp built for the AZI has a dynamic common-mode feedback circuit without signal dependent switches. Three testing circuits using AZI were implemented in 1.2[]m CMOS process at 1.5V power supply voltage. The first testing circuit is a second order fully differential SC bandpass filter working at 5.0MHz sampling rate. The central frequency of the filter was designed at 833KHz and the Q factor is 8. The second testing circuit is a fourth order fully differential SC bandpass delta-sigma modulator with the sampling rate of 5.0MHz too. It has a narrowband of 25KHz centered at the intermediate frequency (IF) of 1.25MHz. The tested results demonstrated a 61dB signal-to-noise-and-distortion-ratio (SNDR) and a -78dBc third order inter-modulation (IM3). The third circuit is a 2-path fully differential fourth order bandpass delta-sigma modulator. It has an effective sampling rate of 10MHz double of the clock rate of 5.0MZ. The signal narrowband of the 2-path modulator is then located at 2.5MHz. The tested results are: 65 dB SNDR, -75dBc IM3, and a -35dBc spurious image of the desired signal. As a supporting and extending research of SC circuits, a new architecture of the SC differentiator having less sensitivity to mismatch and lower thermal noise was also mentioned. A 2-path fourth order SC delta-sigma modulator working at 3.0V supply voltage and 60MHz sampling rate was designed and implemented in 0.35[]m CMOS process. The measured maximal SNR is 76dB for 0.25V (peak differential) sine wave input. |
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| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | x, 81 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilm Inc. |
| Bibliography: | Includes bibliographical references (leaves 71-75). |