rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Semi-reconfigurable data-path
    sub title: design and verification
  name:
    name part: Yang, Zan.
    role:
      role term: creator
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: xx
    date issued: 2001
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    extent: ix, 118 leaves : illustrations ; 28 cm.
  abstract: A number of reconfigurable architectures have been developed in the past decade. For certain applications, such architectures can deliver a higher performance with "on-demand'' formation of necessary hardware functions. However, existing reconfigurable architectures are not suitable for efficiently implementing complex data-path-intensive applications. This study presents a semi-reconfigurable architecture, which is a mixed design of dedicated hardware modules and fine-grain FPGA-like glue-logic resources. This semi-reconfigurable architecture can be employed to implement complex data-path components with reasonable performance and versatility. A case study of floating-point unit and MMX unit is described in this thesis. The semi-reconfigurable data-path consists of two types of building blocks: custom-optimized components, which are mainly complex arithmetic primitives; and an FPGA-like structure, which provides programmable hardware resources to implement glue logic and other non-timing-critical components. Hence the hardware design is also divided into two steps. The first step is to optimize the dedicated hardware modules. A design fusion takes place where similar components of two functional units are identified, repartitioned, scrutinized, and redesigned. This process yields a set of new components that minimize overall circuit area and power consumption. These components can now serve both functional units through reconfiguration. The second step is then to design FPGA-like reconfiguring structure that adjoins these two functional units together. A goal is to reduce the performance loss due to an enhanced versatility associated with reconfigurable structures. Implementation of such design is very complicated. The verification process hence becomes extremely difficult. Two approaches to accelerate this verification process are presented in this thesis. The first approach is code-perturbation simulation that uses application programs as test inputs. The approac…
  note: by Zan Yang.
  note: Vita.
  note: "Major Subject: Electrical Engineering".
  note: Issued also on microfiche from University Microfilm Inc.
  note: Ph. D. Texas A&M University 2001.
  note: Includes bibliographical references (leaves 109-117).
  subject:
    topic: Major electrical engineering
  identifier: 30-11829 UMI
  identifier: http://proxy.library.tamu.edu/login
  related item:
    location:
      url: http://proxy.library.tamu.edu/login
  record info:
    record content source: TXA
    record creation date: 020305
    record change date: 20190325103107.0
    record identifier: in00001669024