A strategy for power estimation and silicon verification /
In recent years, power consumption has become a critical design concern for many VLSI systems. Technology trends and especially portable DSP applications are adding a third dimension, power, to the previously two-dimensional speed and area SOC (System-On-Chip) design space. Low power techniques at...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
2000.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=727853211&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | In recent years, power consumption has become a critical design concern for many VLSI systems. Technology trends and especially portable DSP applications are adding a third dimension, power, to the previously two-dimensional speed and area SOC (System-On-Chip) design space. Low power techniques at different levels ranging from process technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of power conscious tools at these levels. The primary goal of this research is power analysis from an application perspective and to gain insight into the characteristics of the power consumption for range of activities. The characteristics for the power consumption pertain to understanding DSP processor elements and the effects of instruction parallelism on the power consumption. The results of this work will provide a foundation for power optimization efforts and a power profiling simulator. And we propose a unique approach for the estimation of power for core blocks in SOC and a methodology to verify on the silicon. This methodology of simulating RTL for functionality and power dissipation using RTL and power models, enables power estimation in early design phase. This will optimize power at RTL level, synthesis phase of design cycle and sub system/chip IP design in SOC. |
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| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | xi, 156 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilm Inc. |
| Bibliography: | Includes bibliographical references (leaves 82-89). |