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mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Maximizing non-target defect detection using conventional stuck-at fault-based automated test pattern generation tools
  name:
    name part: Grimaila, Michael Russell
    name part: 1965-
    role:
      role term: creator
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: xx
    date issued: 1999
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    extent: xiii, 88 leaves : illustrations ; 28 cm.
  abstract: Testing plays a vital role in determining the success or failure of today's competitive integrated circuit manufacturing business. The cost of test generation, the quality of the applied tests, and the cost of applying the test determine if a product can be profitable in today's marketplace. With product cycle times decreasing and package density increasing, the need for efficient, high quality testing continues to grow. The applied post-manufacturing tests generally consist of a number of different types of tests including conductivity, functional, IDDQ, and static tests. This dissertation will focus upon the static testing of integrated circuits. Accepted commercial practice is to use the stuck-at fault coverage as the metric to measure a test set's quality. As a result, the test pattern length is determined by how many tests are required to attain the desired stuck-at fault coverage. Although a good approximation, test generation based solely upon the stuck-at fault coverage metric is misdirecting the test generation resource. The quality of a test set should not only be based upon the stuck-at fault coverage, but also on its effectiveness at detecting other defect types seen in the real manufacturing process. Although there has been research based upon using more exotic fault models that mimic these real manufacturing defects, test generation using these fault models is too costly in time and memory requirements. Valuable information is lost when using conventional ATPG tools. Our research cuses upon enhancing existing test generation tools by targeting those sites which make the greatest contribution to overall defective part level during the test generation process. For the first time, test pattern generation techniques that maximize non-target defect detection have been successfully used to test a real, 100% scanned, commercial chip consisting of 75,000 logic bates. The results of the experiment proved that the new test generation method yielded defective par…
  note: by Michael Russell Grimaila.
  note: Vita.
  note: "Major Subject: Electrical Engineering".
  note: Issued also on microfiche from University Microfilm Inc.
  note: Ph. D. Texas A&M University 1999.
  note: Includes bibliographical references (leaves 71-75).
  subject:
    topic: Major electrical engineering
  identifier: 99-43492 UMI
  identifier: http://proxy.library.tamu.edu/login
  related item:
    location:
      url: http://proxy.library.tamu.edu/login
  record info:
    record content source: TXA
    record creation date: 000425
    record change date: 20190325093616.0
    record identifier: in00001537992