Testing dynamically reconfigurable FPGAs /
a bottom-up approach. The interconnect resources in
| Main Author: | |
|---|---|
| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1998.
|
| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | a bottom-up approach. The interconnect resources in achieve detection and diagnosis of faults. The PMC addition to the walking-1 test set an "All-0'' test allow the diagnosis of t faulty modules in any are tested. Dynamic and partial reconfiguration is configured to generate test vectors and other modules diagnosability t, which depends upon the number of each direction are tested one by one. The interconnect faults and addressing faults. In this case also, test for stuck-at and bridging faults. A "Walking-1s'' test FPGA. FPGA. Configurations and tests are proposed which FPGAS. Testing methods are also proposed for testing hierarchical block. In each phase, some modules are hierarchical levels are tested. A pair of interconnect In this work, testing methods are proposed to test the ics. interconnect structure of dynamically reconfigurable interconnect. Next, interconnect lines in different interconnect) will be initially tested. A single interface. The CPU interface is tested for stuck-at is coupled with system level diagnosis procedures to is derived. The interconnect structure is tested using lines in each row or column are tested in all phases logic resources and the logic resources available in each hierarchical block, logic resources in the FPGA and the output responses methodology is employed for testing the logic model is applied to each hierarchical block in the modeled faults. All test vectors are generated by the modules. The expression for the maximal value of the resources at the lowest level of hierarchy (local resources of the dynamically reconfigurable FPGA; this responses of the tested modules to the applied test sequence is used for fault detection in each case. In stuck-at fault model is used for the local stuck-at fault model is used to model faults in these the dedicated CPU interface in these FPGAS. A BIST to these vectors are read via the dedicated CPU used extensively to configure the same logic resources vector is used to enable proper diagnosis of the vectors are generated by the logic resources in the vectors are read through the CPU interface. A single with different test generator circuits. The output |
|---|---|
| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | xiii, 121 leaves : illustrations ; 28 cm. Also available online. |
| Bibliography: | Includes bibliographical references (leaves 118-120). |