Multi-level logic minimization through fault dictionary analysis /
algorithm for multi-level logic minimization. This
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1998.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | algorithm for multi-level logic minimization. This analysis is a powerful tool that produces minimization and complimentary to, other methodologies. TALON can As has been noted in (1), adding wires may allow more be used by itself to reduce the size of a logic Data gathered using these techniques show that matrix data, compatible nodes are identified and merged. demonstrably cause conflicting behavior at primary developed in this study, Texas Aggies Logic Optimizing functions are identified and injected. The addition of gated to be eliminated. Using similar fault data to independently. itself leaves many potential reductions undiscovered. Netlister (TALON), is shown to be competitive with, network, or it can be used as a preprocessor or node is a redundant node and that nodes that do not outputs may be compatible. Using fault simulation pairs, which in some cases can then be eliminated. postprocessor for other tools, giving superior results previously published academic work. The algorithm results in selected benchmark circuits superior to any study is based upon the premises that an investable these new implicant functions creates more compatible This thesis presents the results of the study of a new ics. those used to identify compatible bates, implied gate to those obtained by any of them working While offering some improvement, this technique by |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | viii, 35 leaves : illustrations ; 28 cm. Also available online. |
| Bibliography: | Includes bibliographical references (leaves 33-34). |