A new approach to test programmable wiring networks for VLSI /
a simple coloring algorithm and the modified counting
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1998.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | a simple coloring algorithm and the modified counting chips) has made possible the manufacturing of complex digital covered by the path sets generated through the PWN decomposition, a residual adjacency graph processing step is digital programmable chips. The occurrence of faults due to effectiveness of the proposed approach. either shorts or opens in the nets, and stuck-ON/OFF in the FPGAs (field programmable gate arrays), PLDs (programmable has the feature that the indegree is equal to the outdegree. implemented and simulation results have demonstrated the Initially, the given PWN is decomposed into Dp node-disjoint interconnect (wiring network) resources play an important interconnect (wiring network) resources. Therefore, the is proved that it is always possible to decompose a PWN of logic devices) and FPICs (field pro- grammable interconnect lower capacity bounds. Each path set can be tested in maximal degree Dp into Dp node-disjoint path sets if every net in the PWN (except the input nets and the output nets) new approach to test a PWN for fault detection only. The on the testing issues of a PWN. This thesis first presents a path sets by using the maximum flow algorithm with upper and paxallel in a testing phase. Then, for the adjacencies not programmable wiring network (PWN). This thesis concentrates proposed approach employs a divide-and-conquer technique. It role both for programming flexibility and performance of sequence are used to generate the test vectors for each path set. AU algorithms described in this thesis have been switches, is of a major concern. A wiring network can be of systems with a substantial reliance on sophisticated The programmable nature of today's digital circuits such as two types: nonprogrammable wiring network (NPWN) and used to generate additional path sets to test them. Finally, |
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| Item Description: | "Major subject: Computer Science". Vita. |
| Physical Description: | xii, 84 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references: pages 81-82. |