A statistical optimization methodology for practical integrated circuit design for quality and manufacturability /

.This thesis addresses some of the problems encountered in

Bibliographic Details
Main Author:	Pastor, Curtis Lemay
Format:	Thesis eBook
Language:	English
Published:	[Place of publication not identified] : [publisher not identified] ; 1997.
Subjects:	Major electrical engineering.
Online Access:	Link to OAKTrust copy

Description
Summary:	.This thesis addresses some of the problems encountered in 2.simvis95[4]: a utility program for visualization of 3.Optimizations of the circuit under the new process using 3.spectre[5]: Cadence's circuit simulator. 4. 5.Fabrication and packaging of the circuits by MOSIS. 6. accommodate other complex analog circuits. However, and beyond the scope of this research. Once optimized, the are briefly highlighted as follows: 1.Optimization of the artil[l]: Cadence's post-processing tool. circuit will then be manufactured, tested, and compared with development of an all-inclusive methodology is impractical device model which expresses individual MOSFET behavior as a Electrical Engineering Department, Texas A&M University. environment using the MOSIS Design Kit (TM) [2]. fabrication at a later date. This involved the creation of a function of random process variables or noise parameters. Furthermore, certain assumptions will be made along the industrial operational amplifier (OpAmp) for improved manufacture. MOSFETs both physically and statistically under this process. nominal circuit under its original process to determine objective is to develop a methodology to optimize an optimization methodology indeed produces improved optimization. 2.Migration to a new process to facilitate optimized, within the Cadence Design Framework II (TM) [1] performance and reduced variability based upon a statistical performances and reduced circuit variability in accordance research are as follows: 1.GOSSIP[3]: A Generic System for Statistical Design of Analog Integrated Circuits (ICs). The statistical device model (SDM) to accurately represent Statistical Improvement of Performance, developed at the statistical optimization data. Testing of the circuits' performance. The adopted methodology should be general enough to The application of these tools will be demonstrated in The Design for Quality and Manufacturability (DFQM) CAD the new SDM. 4.Layout of the circuits, both nominal and the nominal circuit. Finally, it will be shown that the this thesis as the optimization methodology is described. Throughout this research, several obstacles were overcome to tools, and other software tools used to implement this trade-offs inherent to the design, and feasibility of way which will be noted and discussed. with the models and simulations performed prior to yield the final outcome. The steps taken in this research
Item Description:	"Major subject: Electrical Engineering". Vita.
Physical Description:	xv, 205 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics.
Bibliography:	Includes bibliographical references: pages 137-138.