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mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: System level solutions for analog array processors
  name:
    name part: Han, Gunhee
    name part: 1965-
    role:
      role term: creator
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: xx
    date issued: 1997
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    extent: xiii, 141 leaves : illustrations ; 28 cm.
  abstract: Neural network paradigms and image processing algorithms
  abstract: require intensive parallel computation. Due to its massive
  abstract: parallelism, analog implementation is an attractive approach.
  abstract: This is due, in part, to its low power consumption and small
  abstract: silicon area. However, the analog system is subject to
  abstract: process variations, especially when an array of processing
  abstract: elements is large. More over, the analog system can not
  abstract: physically implement a practical large array. The proposed
  abstract: research is focused to find a system level solution
  abstract: methodology to overcome the practical limits of conventional
  abstract: analog parallel implementations. Since the major building
  abstract: blocks of a neuro-image processor are the multiplier and the
  abstract: integrator, a detailed study on multiplier is performed, and
  abstract: a switched capacitor weighted integrator with offset
  abstract: cancellation is developed. Two types of pseudo-parallel
  abstract: mixed-signal neuro-image processors are developed. One is a
  abstract: "General Purpose Neuro-Image Processor(GPNIP)" which can
  abstract: process a host of neuro-image processing paradigms. This
  abstract: processor adopts a Single Instruction Multiple Data (SIMD)
  abstract: architecture, and multiplexing and pipelining schemes often
  abstract: used in digital systems. Nevertheless, the computation is
  abstract: performed in the discrete-time domain(sampled-data analog
  abstract: signal). The other image processor is a "Pipelined Cellular
  abstract: Neural Network(CNN) Processor". The computation of this
  abstract: processor is performed in the continuous-time domain, i.e.,
  abstract: as a continuous analog signal. The analog processors are
  abstract: fabricated using conventional CMOS technology and
  abstract: experimental results verifying theoretical results are
  abstract: presented. Since the proposed processors are analog array
  abstract: processors, a yield estimation methodology for analog array
  abstract: processor is developed, and then applied to estimate the
  abstract: yield of large CNN processors. These two processor are unique
  abstract: by adopting system level concepts used in digital computation
  abstract: and incorporating them into a mixed-signal pseudo-parallel
  abstract: computation system. The GPNEP has been implemented to be
  abstract: independent of process variation due to a built-in offset
  abstract: cancellation scheme. The architecture allows the gain
  abstract: correction as well. It has a tremendous architectural
  abstract: flexibility, that allows a system designer to implement any
  abstract: architecture based on this processor. Improved computing
  abstract: efficiency and feasibility of large scale mixed-signal neuro
  abstract: image processors are achieved in this research.
  note: by Gunhee Han.
  note: Vita.
  note: "Major Subject: Electrical Engineering".
  note: Issued also on microfiche from University Microfilms Inc.
  note: Includes bibliographical references: pages 123-140.
  note: Ph. D. Texas A&M University 1997.
  subject:
    topic: Major electrical engineering
  identifier: 98-00730 UMI
  identifier: http://proxy.library.tamu.edu/login
  related item:
    location:
      url: http://proxy.library.tamu.edu/login
  record info:
    record content source: TXA
    record creation date: 980403
    record change date: 20190325093459.0
    record identifier: in00001414035