System level solutions for analog array processors /
Neural network paradigms and image processing algorithms
| Main Author: | |
|---|---|
| Format: | Thesis Book |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1997.
|
| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=736580081&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | Neural network paradigms and image processing algorithms require intensive parallel computation. Due to its massive parallelism, analog implementation is an attractive approach. This is due, in part, to its low power consumption and small silicon area. However, the analog system is subject to process variations, especially when an array of processing elements is large. More over, the analog system can not physically implement a practical large array. The proposed research is focused to find a system level solution methodology to overcome the practical limits of conventional analog parallel implementations. Since the major building blocks of a neuro-image processor are the multiplier and the integrator, a detailed study on multiplier is performed, and a switched capacitor weighted integrator with offset cancellation is developed. Two types of pseudo-parallel mixed-signal neuro-image processors are developed. One is a "General Purpose Neuro-Image Processor(GPNIP)" which can process a host of neuro-image processing paradigms. This processor adopts a Single Instruction Multiple Data (SIMD) architecture, and multiplexing and pipelining schemes often used in digital systems. Nevertheless, the computation is performed in the discrete-time domain(sampled-data analog signal). The other image processor is a "Pipelined Cellular Neural Network(CNN) Processor". The computation of this processor is performed in the continuous-time domain, i.e., as a continuous analog signal. The analog processors are fabricated using conventional CMOS technology and experimental results verifying theoretical results are presented. Since the proposed processors are analog array processors, a yield estimation methodology for analog array processor is developed, and then applied to estimate the yield of large CNN processors. These two processor are unique by adopting system level concepts used in digital computation and incorporating them into a mixed-signal pseudo-parallel computation system. The GPNEP has been implemented to be independent of process variation due to a built-in offset cancellation scheme. The architecture allows the gain correction as well. It has a tremendous architectural flexibility, that allows a system designer to implement any architecture based on this processor. Improved computing efficiency and feasibility of large scale mixed-signal neuro image processors are achieved in this research. |
|---|---|
| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | xiii, 141 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references: pages 123-140. |