Switch level optimization for CMOS circuits /
are proposed. Also, algorithms for optimization of both the
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1997.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | are proposed. Also, algorithms for optimization of both the CMOS circuits besides the regular CMOS circuits. CMOS structures. Simulations for power and delay have been CMOS structures. Some of the optimized CMOS structures are comparison to the unoptimized CMOS structures. The above count in the pull-up and the pull-down array of CMOS circuits done in HSPICE [8] for both the optimized and unoptimized for area, delay and power of the optimized and unoptimized in power dissipation and taking less layout area in in the optimized tree in comparison to the original structure In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor of CMOS circuits are proposed. A comparison has been done optimized CMOS structures have been found to be faster, lower pull-up tree and the pull-down tree, based on the above techniques can also be applied to the Pseudo-NMOS and Dynamic techniques, which results in a reduced number of transistors the multiplexers, adders and gray to binary converters. The |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | xii, 97 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |