A 1.8V 10-bit 10MS/sec pipelined ADC /
a 1.2nm standard CMOS process and is tested to be functional.
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1997.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | a 1.2nm standard CMOS process and is tested to be functional. a rate of IOMS/sec. Although the overall architecture of the analog-to-digital converter which operates under a single and comparators, a chip prototype amplifier is fabricated in application is filed for the offset cancelation utilizing capacitive levelshift devices for single-ended amplifiers. concepts used to design important blocks such as amplifiers developed pipelined converter is a general one at the system level, a family of new low-voltage building blocks is of less than the initial specification of 1.8V. To test the products and they are capable of operating at supply levels proposed. The amplifiers and comparators which are designed standard CMOS process and its layout is completed. A patent supply voltage of 1.8V and is capable of resolving 10 bits at The entire converter system is designed using a 0.5/,nm The objective of this thesis is to develop a pipelined to perform interstage processing have high gain-bandwidth |
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| Item Description: | "Major subject: Electrical Engineering". In title, numerals are used. Vita. |
| Physical Description: | xiii, 114 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |