Distributed shared memory multiprocessors using multistage bus networks /
a conventional MIN. To further improve the performance of
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1996.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | a conventional MIN. To further improve the performance of a synchronous packet switched MBN in a distributed shared An analysis of the probabilities of a packet taking different and execution time. By incorporating these policies into an BMIN is obtained through an executiondriven simulation. The Bus Network (MBN) is analyzed in this thesis for a DSM conventional multistage interconnection networks(MINs), cycle-by-cycle simulations with a synthetic workload. The determine the position of a page based on the processor that discussed. The queueing analysis is verified by exhaustive Distributed shared memory (DSM) multiprocessors rely heavily distributing the data over the shared memory and reducing the environment. The MBN avoids some of the shortcomings of the execution time by a certain degree. execution time of various applications on the MBN and the execution-driven simulator, it is shown that the page for most of the applications. The suggested page placement generates the page fault are presented. Two different interleaving policies, high-order and low-order with the page MBN is shown to provide similar performance to BMIN while MBNs support bidirectional routing and there exists a number memory environment is derived and comparison of the results of paths between any source and destination pair. Four self offering simplicity in hardware and more fault-tolerance than on the interconnection network performance. The Multistage placement policies are used to try and better distribute the placement policy with low-order interleaving performs best policies are shown to be effective techniques for request along the path with minimum distance is presented. routes is also derived. Further, the performance analysis of routing techniques are reviewed and an algorithm to route a single bus and hierarchical bus interconnection networks. A static page allocation are studied. Different techniques to switch in a MBN is similar to that in a MIN switch except that there is a single bus connection instead of a crossbar. the DSM multiprocessor, memory management policies based on traffic in the system and reduce the average message latency with those of an equivalent bidirectional MIN (BMLN) is |
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| Item Description: | "Major subject: Computer Science". Vita. |
| Physical Description: | x, 75 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references: pages 71-74. |