Task and instruction scheduling in parallel multithreaded processors /
A new prioritizatioin, technique based on a critical path
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1996.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | A new prioritizatioin, technique based on a critical path and multithreaded architectures: the multiple-instruction- applications chosen carefully to reflect diverse program based analysis of program graphs is shown to enhance based on considerations other than a critical path analysis behavior. Our results suggest the use Of superscalar enhances instruction throughput in a processor by combining from the fetched threads to the multiple functional units of hiding feature of multithreaded architectures. In such instruction throughput significantly by scheduling the best instruction throughput UP to 20% better than previously issue ability of a superscalar processor, and the latency- multithreaded processors in order to Perform efficient of the program graph. Our simulations employ Parallel Parallel muitithreading is a technique to execute parallel Parallel processing. processor Pipelines, and by issuing the best instructions processors, several threads issue instructions to a program parallelism with the strong features of superscalar programs on a multithreaded superscalar processor. It proposed prioritization techniques that employ heuristics superscalar processors multiple functional units every cycle. task and instruction scheduling techniques Yield an the processor. Simulation-based comparisons show that our threads (or tasks) from a parallel Program on to the |
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| Item Description: | "Major subject: Computer Science". Vita. |
| Physical Description: | ix, 60 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references: pages 57-59. |