http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Multi-level logic and performance optimization by Implication analysis
This research introduces and implements a multi-level logic and performance optimization tool called Timing Optimization using Implication analysis (TOI). Multi-level logic optimization is performed to reduce the area of a circuit and performance optimization is performed to reduce the delay of a circuit. TOI uses the transduction method to optimize a circuit. A classification of redundant faults is introduced and applied to the original circuit and the advanced classification method for the transformed circuit is used to remove redundant faults. The concept of pseudo-redundant nodes will be proposed. This concept allows the best implication for maximizing small area and high performance to be chosen. The pseudo-redundant node predictor will be proposed, and used to find the pseudo-redundant nodes. An implication chosen by the pseudo-redundant node predictor is used to transform the circuit. Also, we use a modified Shannon Expansion called the speedup transformation to minimize the incremental delay of the critical path. A performance optimization algorithm using the pseudo-redundant node predictor, the speedup transformation, and the classification technique will be proposed and implemented to minimize both area and delay. Also, a multi-level logic optimization algorithm using these concepts will be proposed to maximize the area reduction.
"Major Subject: Electrical Engineering".
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Includes bibliographical references: pages 68-72.